1. Field of the Invention
The present invention relates to the storage of data, and, more specifically but not exclusively, to writable memory devices such as static random-access memory (SRAM) devices.
2. Description of the Related Art
In a conventional SRAM device, bits of information are stored in an array of memory cells, where the memory cells are arranged in columns and rows. The memory cells in each row are coupled to a word line, and when a reading or writing operation is performed, a pulse is applied to the word line to turn on the access transistors of the memory cells in the row.
To ensure that the duration of the word-line pulse is appropriate (i.e., neither too long nor too short), conventional SRAM devices use tracking circuitry to simulate the amount of time needed to access the memory cells in a row. For example, for write operations, an SRAM device may implement write-tracking circuitry that simulates the amount of time needed for a write operation and to control the duration of the word-line pulse during write operations. If the pulse applied to the word line is not of sufficient time duration and appropriate state, then the writing operation could terminate before data is properly written to the memory array. If, on the other hand, the duration of the pulse applied to the word line is greater than needed, then the memory will be unnecessarily inhibited from continuing on to the next read or write operation, and the performance of the memory device will be unnecessarily slowed.